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Characterization of ultra-thin SOI transistors down to 20nm gate length regime with scanning spreading resistance microscopy (SSRM)

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dc.contributor.authorHartwich, J.
dc.contributor.authorAlvarez, David
dc.contributor.authorDreeskornfeld, L.
dc.contributor.authorSpecht, M.
dc.contributor.authorVandervorst, Wilfried
dc.contributor.authorRisch, Lothar
dc.contributor.imecauthorVandervorst, Wilfried
dc.date.accessioned2021-10-15T04:53:01Z
dc.date.available2021-10-15T04:53:01Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7643
dc.source.conferenceProceedings 33rd European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate16/09/2003
dc.source.conferencelocationEstoril Portugal
dc.title

Characterization of ultra-thin SOI transistors down to 20nm gate length regime with scanning spreading resistance microscopy (SSRM)

dc.typeProceedings paper
dspace.entity.typePublication
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