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A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
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A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
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Date
2022
Journal article
https://doi.org/10.1109/JSSC.2022.3163819
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Moura Santana, Lucas
;
Martens, Ewout
;
Lagos Benites, Jorge
;
Hershberg, Benjamin
;
Wambacq, Piet
;
Craninckx, Jan
Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
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1276
since deposited on 2023-06-15
Acq. date: 2025-12-15
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Metrics
Downloads
601
since deposited on 2023-06-15
98
last month
24
last week
Acq. date: 2025-12-15
Views
1276
since deposited on 2023-06-15
Acq. date: 2025-12-15
Citations