Publication:

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Date

Loading...
Thumbnail Image

Abstract

Description

Statistics

Downloads

1068 since deposited on 2023-06-15
46last month
12last week
Acq. date: 2026-08-07

Views

1283 since deposited on 2023-06-15
3last month
Acq. date: 2026-08-07

Citations

Statistics

Downloads

1068 since deposited on 2023-06-15
46last month
12last week
Acq. date: 2026-08-07

Views

1283 since deposited on 2023-06-15
3last month
Acq. date: 2026-08-07

Citations