Publication:

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Date

2022
Journal article
https://doi.org/10.1109/JSSC.2022.3163819
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dc.contributor.authorMoura Santana, Lucas
dc.contributor.authorMartens, Ewout
dc.contributor.authorLagos Benites, Jorge
dc.contributor.authorHershberg, Benjamin
dc.contributor.authorWambacq, Piet
dc.contributor.authorCraninckx, Jan
dc.contributor.imecauthorMoura Santana, Lucas
dc.contributor.imecauthorMartens, Ewout
dc.contributor.imecauthorLagos Benites, Jorge
dc.contributor.imecauthorHershberg, Benjamin
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecSantana, Lucas Moura::0000-0002-1642-2465
dc.contributor.orcidimecLagos, Jorge::0000-0001-5682-8737
dc.contributor.orcidimecHershberg, Benjamin::0000-0003-3688-2589
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecMartens, Ewout::0000-0001-5485-1837
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecMoura Santana, Lucas::0000-0002-1642-2465
dc.contributor.orcidimecLagos Benites, Jorge::0000-0001-5682-8737
dc.date.accessioned2023-06-15T13:54:00Z
dc.date.available2023-06-15T13:54:00Z
dc.date.embargo2022-07-31
dc.date.issued2022
dc.identifier.doi10.1109/JSSC.2022.3163819
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41735
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage2068
dc.source.endpage2077
dc.source.issue7
dc.source.journalIEEE JOURNAL OF SOLID-STATE CIRCUITS
dc.source.numberofpages10
dc.source.volume57
dc.title

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

dc.typeJournal article
dspace.entity.typePublication
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