On-Chip I/O ESD Protection for GaN-on-SOI Integrated Circuits

Abstract

Gallium Nitride (GaN) platforms are reshaping the efficiency, frequency, and form factor of power electronics integrated circuits. However, the absence of p-channel transistors of GaN technologies makes traditional electrostatic discharge (ESD) protection for integrated circuits (ICs) ineffective. This letter proposes a protection network for input/output pins that leverages the unique conduction properties of enhancement-mode GaN transistors in the third quadrant of their current-voltage (I-V) plane. Experimental measurements confirm the viability of the proposed solution as a library element of the process design kit.