Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions

dc.contributor.author	Sangani, Dishant
dc.contributor.author	Diaz Fortuny, Javier
dc.contributor.author	Bury, Erik
dc.contributor.author	Kaczer, Ben
dc.contributor.author	Gielen, G.
dc.contributor.imecauthor	Sangani, Dishant
dc.contributor.imecauthor	Diaz Fortuny, Javier
dc.contributor.imecauthor	Bury, Erik
dc.contributor.imecauthor	Kaczer, Ben
dc.contributor.orcidimec	Diaz Fortuny, Javier::0000-0002-8186-071X
dc.contributor.orcidimec	Bury, Erik::0000-0002-5847-3949
dc.contributor.orcidimec	Kaczer, Ben::0000-0002-1484-4007
dc.date.accessioned	2023-06-01T12:17:58Z
dc.date.available	2023-05-26T19:52:18Z
dc.date.available	2023-06-01T12:17:58Z
dc.date.issued	2022
dc.identifier.doi	10.1109/IIRW56459.2022.10032756
dc.identifier.eisbn	978-1-6654-5368-4
dc.identifier.issn	1930-8841
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/41648
dc.publisher	IEEE
dc.source.conference	IEEE International Integrated Reliability Workshop (IIRW)
dc.source.conferencedate	OCT 09-14, 2022
dc.source.conferencelocation	South Lake Tahoe
dc.source.journal	na
dc.source.numberofpages	6
dc.title	Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions
dc.type	Proceedings paper
dspace.entity.type	Publication
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