Publication:

A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme

Date

2025
Journal article
https://doi.org/10.1109/JSSC.2024.3416528
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dc.contributor.authorNiu, Shengpu
dc.contributor.authorLambrecht, Joris
dc.contributor.authorWang, Cheng
dc.contributor.authorVerplaetse, Michiel
dc.contributor.authorGu, Ye
dc.contributor.authorCoudyzer, Gertjan
dc.contributor.authorYin, Xin
dc.contributor.imecauthorNiu, Shengpu
dc.contributor.imecauthorLambrecht, Joris
dc.contributor.imecauthorWang, Cheng
dc.contributor.imecauthorVerplaetse, Michiel
dc.contributor.imecauthorGu, Ye
dc.contributor.imecauthorCoudyzer, Gertjan
dc.contributor.imecauthorYin, Xin
dc.contributor.orcidimecNiu, Shengpu::0000-0002-0212-6876
dc.contributor.orcidimecLambrecht, Joris::0000-0001-8291-0339
dc.contributor.orcidimecWang, Cheng::0000-0002-8786-4770
dc.contributor.orcidimecVerplaetse, Michiel::0000-0002-8941-3797
dc.contributor.orcidimecGu, Ye::0000-0002-4903-5170
dc.contributor.orcidimecCoudyzer, Gertjan::0000-0002-3915-394X
dc.contributor.orcidimecYin, Xin::0000-0002-9672-6652
dc.date.accessioned2025-04-29T09:01:21Z
dc.date.available2024-07-16T18:13:21Z
dc.date.available2024-07-31T10:24:52Z
dc.date.available2025-04-29T09:01:21Z
dc.date.embargo2025-01-02
dc.date.issued2025
dc.description.wosFundingTextThis work was supported inpart by the imec High-Speed Transceiver and Coherent Transceiver Programs,European Union (EU)-Funded H2020 Projects POETICS (CoPackaging ofTerabit direct-detection and coherent Optical Engines and switching circuitsin mulTI-Chip moduleS for Datacenter networks and the 5G optical fronthaul)under Grant 871769; in part by the Special Research Fund (BOF) of Ghent University; and in part by the Research Foundation Flanders (FWO).
dc.identifier.doi10.1109/JSSC.2024.3416528
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44164
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage244
dc.source.endpage259
dc.source.issue1
dc.source.journalIEEE JOURNAL OF SOLID-STATE CIRCUITS
dc.source.numberofpages16
dc.source.volume60
dc.subject.keywordsCOUPLED SLOTLINE MODE
dc.subject.keywordsCPW
dc.title

A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme

dc.typeJournal article
dspace.entity.typePublication
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