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Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide
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Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide
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Date
2001
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
van Meer, Hans
;
De Meyer, Kristin
Journal
Solid-State Electronics
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1880
since deposited on 2021-10-14
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last month
Acq. date: 2025-12-15
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Metrics
Views
1880
since deposited on 2021-10-14
2
last month
Acq. date: 2025-12-15
Citations