Publication:
Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide
Date
| dc.contributor.author | van Meer, Hans | |
| dc.contributor.author | De Meyer, Kristin | |
| dc.contributor.imecauthor | De Meyer, Kristin | |
| dc.date.accessioned | 2021-10-14T18:05:54Z | |
| dc.date.available | 2021-10-14T18:05:54Z | |
| dc.date.issued | 2001 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/5743 | |
| dc.source.beginpage | 593 | |
| dc.source.endpage | 598 | |
| dc.source.issue | 4 | |
| dc.source.journal | Solid-State Electronics | |
| dc.source.volume | 45 | |
| dc.title | Threshold voltage model for deep-submicron fully depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
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