Publication:

NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector

Date

2023-02-03
Journal article
https://doi.org/10.1109/LED.2023.3242302
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dc.contributor.authorHiblot, Gaspard
dc.contributor.authorRavsher, Taras
dc.contributor.authorLoo, Roger
dc.contributor.authorYengula Venkata Ramana, Bhuvaneshwari
dc.contributor.authorCanvel, Yann
dc.contributor.authorFranchina Vergel, Nathali
dc.contributor.authorFantini, Andrea
dc.contributor.authorHoushmand Sharifi, Shamin
dc.contributor.authorBazzazian, Nina
dc.contributor.authorAyyad, Mustafa
dc.contributor.authorMerkulov, Alex
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorCouet, Sebastien
dc.contributor.imecauthorHiblot, Gaspard
dc.contributor.imecauthorRavsher, Taras
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorCanvel, Yann
dc.contributor.imecauthorFantini, Andrea
dc.contributor.imecauthorBazzazian, Nina
dc.contributor.imecauthorAyyad, Mustafa
dc.contributor.imecauthorMerkulov, Alex
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorCouet, Sebastien
dc.contributor.imecauthorYengula Venkata Ramana, Bhuvaneshwari
dc.contributor.imecauthorFranchina Vergel, Nathali
dc.contributor.imecauthorHoushmand Sharifi, Shamin
dc.contributor.orcidimecHiblot, Gaspard::0000-0002-3869-965X
dc.contributor.orcidimecRavsher, Taras::0000-0001-7862-5973
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.contributor.orcidimecFantini, Andrea::0000-0002-3220-8856
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecCanvel, Yann::0009-0006-7501-9787
dc.contributor.orcidimecAyyad, Mustafa::0000-0003-2222-8295
dc.contributor.orcidimecMerkulov, Alex::0000-0003-4101-0873
dc.contributor.orcidimecHoushmand Sharifi, Shamin::0000-0002-0989-0666
dc.date.accessioned2024-02-27T08:52:33Z
dc.date.available2023-04-27T04:05:29Z
dc.date.available2023-05-03T06:06:42Z
dc.date.available2024-02-27T08:52:33Z
dc.date.embargo2023-02-03
dc.date.issued2023-02-03
dc.identifier.doi10.1109/LED.2023.3242302
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41487
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage614
dc.source.endpage617
dc.source.issue4
dc.source.journalIEEE ELECTRON DEVICE LETTERS
dc.source.numberofpages4
dc.source.volume44
dc.subject.disciplineElectrical & electronic engineering
dc.title

NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector

dc.typeJournal article
dspace.entity.typePublication
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