Publication:

Optimization of wafer-level low-impedance contact CDM testers

Date

2020
Proceedings Paper
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cris.virtual.orcid0000-0002-3623-1842
cris.virtual.orcid0000-0002-8390-6785
cris.virtual.orcid0000-0002-6481-2951
cris.virtualsource.department894d712a-328b-43e9-8331-871ceac6a4e6
cris.virtualsource.departmenta9297c9a-1d0e-40a3-a8a8-5edf6176ec9a
cris.virtualsource.departmente0386a23-f2bf-4f53-a36f-c1380bca0db7
cris.virtualsource.orcid894d712a-328b-43e9-8331-871ceac6a4e6
cris.virtualsource.orcida9297c9a-1d0e-40a3-a8a8-5edf6176ec9a
cris.virtualsource.orcide0386a23-f2bf-4f53-a36f-c1380bca0db7
dc.contributor.authorSimicic, Marko
dc.contributor.authorWu, Wei-Min
dc.contributor.authorJack, Nathan
dc.contributor.authorTamura, Shinichi
dc.contributor.authorShimada, Yohei
dc.contributor.authorSawada, Masanori
dc.contributor.authorChen, Shih-Hung
dc.contributor.imecauthorSimicic, Marko
dc.contributor.imecauthorWu, Wei-Min
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.orcidimecSimicic, Marko::0000-0002-3623-1842
dc.date.accessioned2021-10-29T04:08:19Z
dc.date.available2021-10-29T04:08:19Z
dc.date.issued2020
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35946
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9241215
dc.source.conferenceEOS/ESD Symposium
dc.source.conferencedate13/09/2020
dc.source.conferencelocationReno, NV USA
dc.title

Optimization of wafer-level low-impedance contact CDM testers

dc.typeProceedings paper
dspace.entity.typePublication
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