A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures

dc.contributor.author	Lofrano, Melina
dc.contributor.author	Gonzalez, Mario
dc.contributor.author	Vandevelde, Bart
dc.contributor.imecauthor	Lofrano, Melina
dc.contributor.imecauthor	Gonzalez, Mario
dc.contributor.imecauthor	Vandevelde, Bart
dc.contributor.orcidimec	Vandevelde, Bart::0000-0002-6753-6438
dc.date.accessioned	2021-10-22T03:13:48Z
dc.date.available	2021-10-22T03:13:48Z
dc.date.embargo	9999-12-31
dc.date.issued	2014
dc.identifier.issn	0167-9317
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/24162
dc.identifier.url	http://www.sciencedirect.com/science/article/pii/S016793171300693X
dc.source.beginpage	85
dc.source.endpage	89
dc.source.journal	Microelectronic Engineering
dc.source.volume	120
dc.title	A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures
dc.type	Journal article
dspace.entity.type	Publication
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