Publication:

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

Date

2015
Proceedings Paper
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dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorDekkers, Harold
dc.contributor.authorSchram, Tom
dc.contributor.authorChew, Soon Aik
dc.contributor.authorParvais, Bertrand
dc.contributor.authorDehan, Morin
dc.contributor.authorDevriendt, Katia
dc.contributor.authorTao, Zheng
dc.contributor.authorSebaai, Farid
dc.contributor.authorBaerts, Christina
dc.contributor.authorVan Elshocht, Sven
dc.contributor.authorYoshida, Naomi
dc.contributor.authorPhatak, Anup
dc.contributor.authorLazik, Christoph
dc.contributor.authorBrand, Adam
dc.contributor.authorClark, William
dc.contributor.authorFried, David
dc.contributor.authorMocuta, Dan
dc.contributor.authorBarla, Kathy
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorDekkers, Harold
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorBaerts, Christina
dc.contributor.imecauthorVan Elshocht, Sven
dc.contributor.imecauthorBarla, Kathy
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecDekkers, Harold::0000-0003-4778-5709
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecVan Elshocht, Sven::0000-0002-6512-1909
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-22T22:04:13Z
dc.date.available2021-10-22T22:04:13Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25793
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7223656
dc.source.beginpage148
dc.source.conferenceSymposium on VLSI Technology
dc.source.conferencedate15/06/2015
dc.source.conferencelocationKyoto Japan
dc.source.endpage149
dc.title

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

dc.typeProceedings paper
dspace.entity.typePublication
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