DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM

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Author(s)

Matagne, Philippe

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Kikuchi, Yoshiaki

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Huynh Bao, Trong

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Devriendt, Katia

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Ragnarsson, Lars-Ake

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Boemmels, Juergen

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Mallik, Arindam

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Altamirano Sanchez, Efrain

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Lorant, Christophe

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Jourdan, Nicolas

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Porret, Clément

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Metrics

1 since deposited on 2021-10-25

Acq. date: 2025-12-08

1991 since deposited on 2021-10-25

Acq. date: 2025-12-08