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DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM

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dc.contributor.authorMatagne, Philippe
dc.contributor.authorNakamura, H.
dc.contributor.authorKim, Min-Soo
dc.contributor.authorKikuchi, Yoshiaki
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorTao, Zheng
dc.contributor.authorLi, Waikin
dc.contributor.authorDevriendt, Katia
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorMallik, Arindam
dc.contributor.authorAltamirano Sanchez, Efrain
dc.contributor.authorSebaai, Farid
dc.contributor.authorLorant, Christophe
dc.contributor.authorJourdan, Nicolas
dc.contributor.authorPorret, Clément
dc.contributor.authorMocuta, Dan
dc.contributor.authorHarada, N.
dc.contributor.authorMatsuoka, F.
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorKim, Min-Soo
dc.contributor.imecauthorKikuchi, Yoshiaki
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorLi, Waikin
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorBoemmels, Juergen
dc.contributor.imecauthorMallik, Arindam
dc.contributor.imecauthorAltamirano Sanchez, Efrain
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorLorant, Christophe
dc.contributor.imecauthorJourdan, Nicolas
dc.contributor.imecauthorPorret, Clément
dc.contributor.orcidimecKim, Min-Soo::0000-0003-0211-0847
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecMallik, Arindam::0000-0002-0742-9366
dc.contributor.orcidimecLorant, Christophe::0000-0001-7363-9348
dc.contributor.orcidimecPorret, Clément::0000-0002-4561-348X
dc.date.accessioned2021-10-25T23:10:17Z
dc.date.available2021-10-25T23:10:17Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31309
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8551632
dc.source.beginpage45
dc.source.conference2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
dc.source.conferencedate24/09/2018
dc.source.conferencelocationAustin, TX USA
dc.source.endpage48
dc.title

DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM

dc.typeProceedings paper
dspace.entity.typePublication
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