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Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistors
Publication:
Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistors
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Date
2019
Proceedings Paper
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41888.pdf
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Verreck, Devin
;
Arutchelvan, Goutham
;
Heyns, Marc
;
Radu, Iuliana
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1915
since deposited on 2021-10-27
Acq. date: 2025-12-15
Citations
Metrics
Views
1915
since deposited on 2021-10-27
Acq. date: 2025-12-15
Citations