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Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistors

Date

2019
Proceedings Paper
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dc.contributor.authorVerreck, Devin
dc.contributor.authorArutchelvan, Goutham
dc.contributor.authorHeyns, Marc
dc.contributor.authorRadu, Iuliana
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorArutchelvan, Goutham
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.date.accessioned2021-10-27T22:42:46Z
dc.date.available2021-10-27T22:42:46Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34378
dc.source.beginpage283
dc.source.conference24th International Conference on Simulation of Semiconductor Processes and Devices - SISPAD
dc.source.conferencedate4/09/2019
dc.source.conferencelocationUdine Italy
dc.source.endpage286
dc.title

Device and circuit level gate configuration optimization for monolayer 2D material feld-effect transistors

dc.typeProceedings paper
dspace.entity.typePublication
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