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A 12mW 10GHz FMCW PLL based on an integrating DAC with 90kHz rms frequency error for 23MHz/µs slope and 1.2GHz chirp bandwidth
Publication:
A 12mW 10GHz FMCW PLL based on an integrating DAC with 90kHz rms frequency error for 23MHz/µs slope and 1.2GHz chirp bandwidth
Date
2020
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Renukaswamy, Pratap
;
Markulic, Nereo
;
Park, Sehoon
;
Kankuppe Raghavendra Swamy, Anirudh Praveen
;
Wambacq, Piet
;
Craninckx, Jan
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2035
since deposited on 2021-10-29
Acq. date: 2025-10-27
Citations
Metrics
Views
2035
since deposited on 2021-10-29
Acq. date: 2025-10-27
Citations