Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

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Published version 2.83 MB

Author(s)

Acharya, Lomash Chandra

;

;

;

Singh, Khoirom Johnson

;

Dargupally, Mahipal

;

Shabarish, Nayakanti Sai

;

;

Ramakrishnan, Venkatraman

;

Dasgupta, Sudeb

;

Journal

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

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1071 since deposited on 2023-08-11

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Acq. date: 2025-10-25