Publication:

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

Date

2023
Journal article
https://doi.org/10.1109/TCAD.2022.3231173
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dc.contributor.authorAcharya, Lomash Chandra
dc.contributor.authorSharma, Arvind
dc.contributor.authorMishra, Neeraj
dc.contributor.authorSingh, Khoirom Johnson
dc.contributor.authorDargupally, Mahipal
dc.contributor.authorShabarish, Nayakanti Sai
dc.contributor.authorMandal, Ajoy
dc.contributor.authorRamakrishnan, Venkatraman
dc.contributor.authorDasgupta, Sudeb
dc.contributor.authorBulusu, Anand
dc.contributor.imecauthorSharma, Arvind
dc.contributor.orcidimecSharma, Arvind::0000-0002-9250-9642
dc.date.accessioned2023-10-17T13:10:05Z
dc.date.available2023-08-11T16:46:01Z
dc.date.available2023-10-17T13:10:05Z
dc.date.embargo9999-12-31
dc.date.issued2023
dc.description.wosFundingTexthis work was supported by the Semiconductor Research Corporation (SRC) under IRP task-2864.001.
dc.identifier.doi10.1109/TCAD.2022.3231173
dc.identifier.issn0278-0070
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42321
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage2657
dc.source.endpage2663
dc.source.issue8
dc.source.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
dc.source.numberofpages7
dc.source.volume42
dc.subject.keywordsNBTI
dc.subject.keywordsDELAY
dc.subject.keywordsCHALLENGES
dc.title

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

dc.typeJournal article
dspace.entity.typePublication
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