Defect generation in ultra-thin SiO2 gate layers and SiO2/ZrO2 gate stacks and the dispersive transport model

dc.contributor.author	Houssa, Michel
dc.contributor.author	Afanas'ev, V. V.
dc.contributor.author	Stesmans, Andre
dc.contributor.author	Heyns, Marc
dc.contributor.imecauthor	Houssa, Michel
dc.contributor.imecauthor	Stesmans, Andre
dc.contributor.imecauthor	Heyns, Marc
dc.contributor.orcidimec	Houssa, Michel::0000-0003-1844-3515
dc.date.accessioned	2021-10-14T17:02:47Z
dc.date.available	2021-10-14T17:02:47Z
dc.date.issued	2001
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/5348
dc.source.beginpage	367
dc.source.endpage	372
dc.source.issue	1_4
dc.source.journal	Microelectronic Engineering
dc.source.volume	59
dc.title	Defect generation in ultra-thin SiO2 gate layers and SiO2/ZrO2 gate stacks and the dispersive transport model
dc.type	Journal article
dspace.entity.type	Publication
Files
Publication available in collections:	Articles

Date