Publication:

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology

Date

2018
Proceedings Paper
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dc.contributor.authorSimicic, Marko
dc.contributor.authorHellings, Geert
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorLinten, Dimitri
dc.contributor.imecauthorSimicic, Marko
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.orcidimecSimicic, Marko::0000-0002-3623-1842
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.date.accessioned2021-10-26T03:51:29Z
dc.date.available2021-10-26T03:51:29Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31779
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8486885
dc.source.beginpage194
dc.source.conference48th European Solid-State Device Research Conference - ESSDERC
dc.source.conferencedate3/09/2018
dc.source.conferencelocationDresden Germany
dc.source.endpage197
dc.title

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology

dc.typeProceedings paper
dspace.entity.typePublication
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