Publication:

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Date

2022
Proceedings Paper
https://doi.org/10.1117/12.2615641
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Author(s)

Gupta, Anshul  
;
Tao, Zheng  
;
Radisic, Dunja  
;
Mertens, Hans  
;
Varela Pedreira, Olalla  
;
Demuynck, Steven  
;
Boemmels, Juergen  
;
Devriendt, Katia  
;
Heylen, Nancy  
;
Wang, Shouhua  
;
Kenis, Karine  
;
Teugels, Lieve  
;
Sebaai, Farid  
;
Lorant, Christophe  
;
Jourdan, Nicolas  
;
Chan, BT  
;
Subramanian, Sujith  
;
Schleicher, Filip  
;
Peter, Antony  
;
Rassoul, Nouredine  
;
Siew, Yong Kong  
;
Briggs, Basoene  
;
Zhou, Daisy  
;
Rosseel, Erik  
;
Capogreco, Elena  
;
Mannaert, Geert  
;
Sepulveda Marquez, Alfonso  
;
Dupuy, Emmanuel  
;
Vandersmissen, Kevin  
;
Chehab, Bilal  
;
Murdoch, Gayle  
;
Altamirano Sanchez, Efrain  
;
Biesemans, Serge  
;
Tokei, Zsolt  
;
Dentoni Litta, Eugenio  
;
Horiguchi, Naoto  

Journal

Proceedings of SPIE

Abstract

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1339 since deposited on 2022-09-08
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1339 since deposited on 2022-09-08
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Acq. date: 2025-12-11

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