Publication:

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Date

2022
Proceedings Paper
https://doi.org/10.1117/12.2615641
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dc.contributor.authorGupta, Anshul
dc.contributor.authorTao, Zheng
dc.contributor.authorRadisic, Dunja
dc.contributor.authorMertens, Hans
dc.contributor.authorVarela Pedreira, Olalla
dc.contributor.authorDemuynck, Steven
dc.contributor.authorBoemmels, Juergen
dc.contributor.authorDevriendt, Katia
dc.contributor.authorHeylen, Nancy
dc.contributor.authorWang, Shouhua
dc.contributor.authorKenis, Karine
dc.contributor.authorTeugels, Lieve
dc.contributor.authorSebaai, Farid
dc.contributor.authorLorant, Christophe
dc.contributor.authorJourdan, Nicolas
dc.contributor.authorChan, BT
dc.contributor.authorSubramanian, Sujith
dc.contributor.authorSchleicher, Filip
dc.contributor.authorPeter, Antony
dc.contributor.authorRassoul, Nouredine
dc.contributor.imecauthorGupta, Anshul
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorRadisic, Dunja
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorVarela Pedreira, Olalla
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorBoemmels, Juergen
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorHeylen, Nancy
dc.contributor.imecauthorWang, Shouhua
dc.contributor.imecauthorKenis, Karine
dc.contributor.imecauthorTeugels, Lieve
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorLorant, Christophe
dc.contributor.imecauthorJourdan, Nicolas
dc.contributor.imecauthorChan, BT
dc.contributor.imecauthorSubramanian, Sujith
dc.contributor.imecauthorSchleicher, Filip
dc.contributor.imecauthorPeter, Antony
dc.contributor.imecauthorRassoul, Nouredine
dc.contributor.orcidimecVarela Pedreira, Olalla::0000-0002-2987-1972
dc.contributor.orcidimecBoemmels, Juergen::0000-0002-8761-5213
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecWang, Shouhua::0000-0002-9105-8552
dc.contributor.orcidimecTeugels, Lieve::0000-0002-6613-9414
dc.contributor.orcidimecLorant, Christophe::0000-0001-7363-9348
dc.contributor.orcidimecChan, BT::0000-0003-2890-0388
dc.contributor.orcidimecSubramanian, Sujith::0000-0001-8938-9750
dc.contributor.orcidimecSchleicher, Filip::0000-0003-3630-7285
dc.contributor.orcidimecPeter, Antony::0000-0001-5941-0563
dc.contributor.orcidimecRassoul, Nouredine::0000-0001-9489-3396
dc.contributor.orcidimecSepulveda Marquez, Alfonso::0000-0003-4726-177X
dc.contributor.orcidimecDupuy, Emmanuel::0000-0003-3341-1618
dc.contributor.orcidimecAltamirano Sanchez, Efrain::0000-0003-3235-6055
dc.contributor.orcidimecDentoni Litta, Eugenio::0000-0003-0333-376X
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2023-04-26T08:46:58Z
dc.date.available2022-09-08T02:38:37Z
dc.date.available2023-04-26T08:46:58Z
dc.date.issued2022
dc.identifier.doi10.1117/12.2615641
dc.identifier.eisbn978-1-5106-4988-0
dc.identifier.isbn978-1-5106-4987-3
dc.identifier.issn0277-786X
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40366
dc.publisherSPIE-INT SOC OPTICAL ENGINEERING
dc.source.beginpage120560B
dc.source.conferenceConference on Advanced Etch Technology and Process Integration for Nanopatterning XI Part of SPIE Advanced Lithography and Patterning Conference
dc.source.conferencedateAPR 24-MAY 27, 2020-2022
dc.source.conferencelocationSan Jose
dc.source.journalProceedings of SPIE
dc.source.numberofpages5
dc.source.volume12056
dc.title

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

dc.typeProceedings paper
dspace.entity.typePublication
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