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The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
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The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
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Date
2017
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Appeltans, Raf
;
Weckx, Pieter
;
Raghavan, Praveen
;
Kim, Ryan Ryoung han
;
Kar, Gouri Sankar
;
Furnemont, Arnaud
;
Van der Perre, Liesbet
;
Dehaene, Wim
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1873
since deposited on 2021-10-24
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Acq. date: 2025-12-16
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Metrics
Views
1873
since deposited on 2021-10-24
1
last month
Acq. date: 2025-12-16
Citations