Publication:

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7

Date

2017
Proceedings Paper
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dc.contributor.authorAppeltans, Raf
dc.contributor.authorWeckx, Pieter
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorAppeltans, Raf
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.date.accessioned2021-10-24T02:52:49Z
dc.date.available2021-10-24T02:52:49Z
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27758
dc.identifier.urlhttp://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2613275
dc.source.beginpage101480G
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XI
dc.source.conferencedate26/02/2017
dc.source.conferencelocationSan Jose, CA USA
dc.title

The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7

dc.typeProceedings paper
dspace.entity.typePublication
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