Publication:
Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0001-6465-7157 | |
| cris.virtual.orcid | 0000-0002-5058-8303 | |
| cris.virtual.orcid | 0000-0001-7325-8836 | |
| cris.virtualsource.department | eb275c74-aac2-41cf-8eea-eb57ee1fc661 | |
| cris.virtualsource.department | 8a303854-e9b4-460a-b79d-03df3b3c4394 | |
| cris.virtualsource.department | 52be9e5e-be21-4e16-bad5-1335c497e6fd | |
| cris.virtualsource.orcid | eb275c74-aac2-41cf-8eea-eb57ee1fc661 | |
| cris.virtualsource.orcid | 8a303854-e9b4-460a-b79d-03df3b3c4394 | |
| cris.virtualsource.orcid | 52be9e5e-be21-4e16-bad5-1335c497e6fd | |
| dc.contributor.author | Chuang, Po-Yao | |
| dc.contributor.author | Lorenzelli, Francesco | |
| dc.contributor.author | Wu, Cheng-Wen | |
| dc.contributor.author | Marinissen, Erik Jan | |
| dc.contributor.imecauthor | Chuang, Po-Yao | |
| dc.contributor.imecauthor | Lorenzelli, Francesco | |
| dc.contributor.imecauthor | Marinissen, Erik Jan | |
| dc.contributor.orcidimec | Chuang, Po-Yao::0000-0001-7325-8836 | |
| dc.contributor.orcidimec | Lorenzelli, Francesco::0000-0001-6465-7157 | |
| dc.contributor.orcidimec | Marinissen, Erik Jan::0000-0002-5058-8303 | |
| dc.date.accessioned | 2025-03-17T19:25:47Z | |
| dc.date.available | 2025-03-17T19:25:47Z | |
| dc.date.issued | 2025-MAR | |
| dc.identifier.doi | 10.1109/TCAD.2024.3466809 | |
| dc.identifier.issn | 0278-0070 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/45414 | |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |
| dc.source.beginpage | 1155 | |
| dc.source.endpage | 1168 | |
| dc.source.issue | 3 | |
| dc.source.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | |
| dc.source.numberofpages | 14 | |
| dc.source.volume | 44 | |
| dc.title | Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
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