Publication:

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency

Date

2025-MAR
Journal article
https://doi.org/10.1109/TCAD.2024.3466809
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dc.contributor.authorChuang, Po-Yao
dc.contributor.authorLorenzelli, Francesco
dc.contributor.authorWu, Cheng-Wen
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.imecauthorChuang, Po-Yao
dc.contributor.imecauthorLorenzelli, Francesco
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecChuang, Po-Yao::0000-0001-7325-8836
dc.contributor.orcidimecLorenzelli, Francesco::0000-0001-6465-7157
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2025-03-17T19:25:47Z
dc.date.available2025-03-17T19:25:47Z
dc.date.issued2025-MAR
dc.identifier.doi10.1109/TCAD.2024.3466809
dc.identifier.issn0278-0070
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45414
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage1155
dc.source.endpage1168
dc.source.issue3
dc.source.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
dc.source.numberofpages14
dc.source.volume44
dc.title

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency

dc.typeJournal article
dspace.entity.typePublication
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