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A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric

Date

2001
Proceedings Paper
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dc.contributor.authorVerheyen, Peter
dc.contributor.authorCollaert, Nadine
dc.contributor.authorCaymax, Matty
dc.contributor.authorLoo, Roger
dc.contributor.authorVan Rossum, Marc
dc.contributor.authorDe Meyer, Kristin
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorCaymax, Matty
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.date.accessioned2021-10-14T18:19:04Z
dc.date.available2021-10-14T18:19:04Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5811
dc.source.beginpage15
dc.source.conferenceInternational Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers
dc.source.conferencedate18/04/2001
dc.source.conferencelocationHsinchu Japan
dc.source.endpage18
dc.title

A 50 nm vertical Si0.70/Ge0.30/Si0.85/Ge0.15 pMOSFET with an oxide/nitride gate dielectric

dc.typeProceedings paper
dspace.entity.typePublication
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