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Mechanism of positive-bias temperature instability in sub-1 nm TaN/HfN/HfO2 gate stack with low preexisting traps

Date

2005-09
Journal article
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dc.contributor.authorSa, N.
dc.contributor.authorKang, J.F.
dc.contributor.authorYang, H.
dc.contributor.authorLiu, X.Y.
dc.contributor.authorHe, Y.D.
dc.contributor.authorHan, R.Q.
dc.contributor.authorRen, C.
dc.contributor.authorYu, HongYu
dc.contributor.authorChan, D.S.H.
dc.contributor.authorKwong, D.-L.
dc.date.accessioned2021-10-16T04:45:08Z
dc.date.available2021-10-16T04:45:08Z
dc.date.issued2005-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11148
dc.source.beginpage610
dc.source.endpage612
dc.source.issue26
dc.source.journalIEEE Electron Device Letters
dc.source.volume9
dc.title

Mechanism of positive-bias temperature instability in sub-1 nm TaN/HfN/HfO2 gate stack with low preexisting traps

dc.typeJournal article
dspace.entity.typePublication
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