Publication:

Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

Date

2024
Journal article
https://doi.org/10.1002/inf2.12490
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dc.contributor.authorNiu, Jingjie
dc.contributor.authorJeon, Sumin
dc.contributor.authorKim, Donggyu
dc.contributor.authorBaek, Sungpyo
dc.contributor.authorYoo, Hyun Ho
dc.contributor.authorLi, Jie
dc.contributor.authorPark, Ji-Sang
dc.contributor.authorLee, Yoonmyung
dc.contributor.authorLee, Sungjoo
dc.contributor.imecauthorLi, Jie
dc.date.accessioned2024-09-24T09:37:09Z
dc.date.available2023-11-12T17:45:48Z
dc.date.available2024-09-24T09:37:09Z
dc.date.embargo2023-11-02
dc.date.issued2024
dc.description.wosFundingTextThis research was supported by the Basic Science Research Program through the National Research Foundation of Korea and was funded by the Korean government (MSIP) (Grant Nos. RS-2023-00281048, 2022R1A2C3003068, 2022M3F3A2A01072215). This study was supported by Samsung Electronics Co., Ltd. (IO201215-08197-01).
dc.identifier.doi10.1002/inf2.12490
dc.identifier.issn2567-3165
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43144
dc.publisherWILEY
dc.source.beginpageArt. e12490
dc.source.endpageN/A
dc.source.issue2
dc.source.journalINFOMAT
dc.source.numberofpages11
dc.source.volume6
dc.subject.keywordsFIELD-EFFECT TRANSISTORS
dc.subject.keywordsINPLANE
dc.title

Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

dc.typeJournal article
dspace.entity.typePublication
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