Publication:

Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

Date

2011
Proceedings Paper
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dc.contributor.authorWitters, Liesbeth
dc.contributor.authorMitard, Jerome
dc.contributor.authorVeloso, Anabela
dc.contributor.authorHikavyy, Andriy
dc.contributor.authorFranco, Jacopo
dc.contributor.authorKauerauf, Thomas
dc.contributor.authorCho, Moon Ju
dc.contributor.authorSchram, Tom
dc.contributor.authorSebaai, Farid
dc.contributor.authorYamaguchi, Shinpei
dc.contributor.authorTakeoka, S.
dc.contributor.authorFukuda, Masahiro
dc.contributor.authorWang, Wei-E
dc.contributor.authorDuriez, Blandine
dc.contributor.authorEneman, Geert
dc.contributor.authorLoo, Roger
dc.contributor.authorKellens, Kristof
dc.contributor.authorTielens, Hilde
dc.contributor.authorFavia, Paola
dc.contributor.authorRohr, Erika
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorHikavyy, Andriy
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorSebaai, Farid
dc.contributor.imecauthorDuriez, Blandine
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorKellens, Kristof
dc.contributor.imecauthorTielens, Hilde
dc.contributor.imecauthorFavia, Paola
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorRoussel, Philippe
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorMannaert, Geert
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecHikavyy, Andriy::0000-0002-8201-075X
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.contributor.orcidimecFavia, Paola::0000-0002-1019-3497
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecRoussel, Philippe::0000-0002-0402-8225
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-19T21:52:30Z
dc.date.available2021-10-19T21:52:30Z
dc.date.embargo9999-12-31
dc.date.issued2011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20155
dc.source.beginpage654
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate5/12/2011
dc.source.conferencelocationWashington, DC USA
dc.source.endpage657
dc.title

Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

dc.typeProceedings paper
dspace.entity.typePublication
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