Publication:

Impact of gate stack dielectric on intrinsic voltage gain and low frequency noise in Ge pMOSFETs

Date

2015
Proceedings Paper
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dc.contributor.authorOliveira, A.V.
dc.contributor.authorAgopian, P.G.D.
dc.contributor.authorMartino, J.A.
dc.contributor.authorFang, Wen
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorMitard, Jerome
dc.contributor.authorMertens, Hans
dc.contributor.authorSimoen, Eddy
dc.contributor.authorMocuta, Anda
dc.contributor.authorCollaert, Nadine
dc.contributor.authorThean, Aaron
dc.contributor.authorClaeys, Cor
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-22T21:27:59Z
dc.date.available2021-10-22T21:27:59Z
dc.date.embargo9999-12-31
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25704
dc.identifier.urlhttps://doi.org/10.1149/06605.0309ecst
dc.source.beginpage309
dc.source.conferenceAdvanced CMOS-Compatible Semiconductor Devices 17
dc.source.conferencedate24/05/2015
dc.source.conferencelocationChicago, IL USA
dc.source.endpage314
dc.title

Impact of gate stack dielectric on intrinsic voltage gain and low frequency noise in Ge pMOSFETs

dc.typeProceedings paper
dspace.entity.typePublication
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