Publication:

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

Date

2021-11-04
Proceedings Paper
https://doi.org/10.1109/SLIP52707.2021.00011
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dc.contributor.authorSisto, Giuliano
dc.contributor.authorChen, Rongmei
dc.contributor.authorChou, Richard
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorBeyne, Eric
dc.contributor.authorRod Metcalfe
dc.contributor.authorMilojevic, Dragomir
dc.contributor.imecauthorChen, Rongmei
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2022-07-05T09:26:22Z
dc.date.available2022-03-26T02:08:17Z
dc.date.available2022-07-04T07:37:46Z
dc.date.available2022-07-05T09:26:22Z
dc.date.embargo9999-12-31
dc.date.issued2021-11-04
dc.identifier.doi10.1109/SLIP52707.2021.00011
dc.identifier.eisbn978-1-6654-0083-1
dc.identifier.issn1544-5623
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39525
dc.publisherIEEE COMPUTER SOC
dc.source.beginpage17
dc.source.conference23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP)
dc.source.conferencedateNOV 04, 2021
dc.source.conferencelocationMunich, Germany
dc.source.endpage23
dc.source.journalna
dc.source.numberofpages7
dc.subject.keywords3D EDA flow
dc.title

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)

dc.typeProceedings paper
dspace.entity.typePublication
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