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A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

Date

2004
Proceedings Paper
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dc.contributor.authorWang, Hua
dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorMiranda, Miguel
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-15T17:48:54Z
dc.date.available2021-10-15T17:48:54Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9899
dc.source.beginpage759
dc.source.conferenceProceedings Asia and South Pacific Design Automation Conference - ASP-DAC
dc.source.conferencedate27/01/2004
dc.source.conferencelocationYokohama Japan
dc.source.endpage761
dc.title

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

dc.typeProceedings paper
dspace.entity.typePublication
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