Publication:

Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits

Date

2009
Proceedings Paper
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dc.contributor.authorRadisic, Alex
dc.contributor.authorLuhn, Ole
dc.contributor.authorSwinnen, Bart
dc.contributor.authorBender, Hugo
dc.contributor.authorDrijbooms, Chris
dc.contributor.authorDoumen, Geert
dc.contributor.authorKellens, Kristof
dc.contributor.authorRuythooren, Wouter
dc.contributor.authorVereecken, Philippe
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorDrijbooms, Chris
dc.contributor.imecauthorDoumen, Geert
dc.contributor.imecauthorKellens, Kristof
dc.contributor.imecauthorRuythooren, Wouter
dc.contributor.imecauthorVereecken, Philippe
dc.contributor.orcidimecVereecken, Philippe::0000-0003-4115-0075
dc.date.accessioned2021-10-18T02:01:46Z
dc.date.available2021-10-18T02:01:46Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16069
dc.identifier.urlhttp://www.mrs.org/s_mrs/sec_subscribe.asp?CID=16750&DID=231997&action=detail
dc.source.beginpage1112-E03-06
dc.source.conferenceMaterials and Technologies for 3-D Integration
dc.source.conferencedate1/12/2008
dc.source.conferencelocationBoston, MA USA
dc.title

Cu Plating of Through-Si Vias for 3D-Stacked Integrated Circuits

dc.typeProceedings paper
dspace.entity.typePublication
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