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An analysis of the reliability of a wafer level package (WLP) using a silicon under the bump (SUB) configuration

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dc.contributor.authorGonzalez, Mario
dc.contributor.authorVandevelde, Bart
dc.contributor.authorVanden Bulcke, Mathieu
dc.contributor.authorWinters, Christophe
dc.contributor.authorBeyne, Eric
dc.contributor.authorLee, Y.J.
dc.contributor.authorHarkness, B.R.
dc.contributor.authorMohamed, M.
dc.contributor.authorMeynen, H.
dc.contributor.authorVanlathem, E.
dc.contributor.imecauthorGonzalez, Mario
dc.contributor.imecauthorVandevelde, Bart
dc.contributor.imecauthorVanden Bulcke, Mathieu
dc.contributor.imecauthorWinters, Christophe
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecVandevelde, Bart::0000-0002-6753-6438
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2021-10-15T04:48:41Z
dc.date.available2021-10-15T04:48:41Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7618
dc.source.beginpage858
dc.source.conferenceProceedings of the 53rd Electronic Components and Technology Conference
dc.source.conferencedate27/05/2003
dc.source.conferencelocationNew Orleans, LA USA
dc.source.endpage863
dc.title

An analysis of the reliability of a wafer level package (WLP) using a silicon under the bump (SUB) configuration

dc.typeProceedings paper
dspace.entity.typePublication
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