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Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid
Publication:
Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid
Date
2022-05-26
Proceedings Paper
https://doi.org/10.1117/12.2614260
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spie2022_stag_via_paper_9.pdf
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Woltgens, Pieter
;
Colina, Alberto
;
Rio, David
;
Delorme, Max
;
Kovalevich, Tatiana
;
Thiam, Arame
;
Van Roey, Frieda
;
Zografos, Odysseas
Journal
SPIE Proceedings Vol. 12051: Optical and EUV Nanolithography XXXV
Abstract
Description
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180
since deposited on 2022-09-19
Acq. date: 2025-10-24
Views
1459
since deposited on 2022-09-19
Acq. date: 2025-10-24
Citations
Metrics
Downloads
180
since deposited on 2022-09-19
Acq. date: 2025-10-24
Views
1459
since deposited on 2022-09-19
Acq. date: 2025-10-24
Citations