Publication:

Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

Date

2022-05-26
Proceedings Paper
https://doi.org/10.1117/12.2614260
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dc.contributor.authorWoltgens, Pieter
dc.contributor.authorColina, Alberto
dc.contributor.authorRio, David
dc.contributor.authorDelorme, Max
dc.contributor.authorKovalevich, Tatiana
dc.contributor.authorThiam, Arame
dc.contributor.authorVan Roey, Frieda
dc.contributor.authorZografos, Odysseas
dc.contributor.imecauthorDelorme, Max
dc.contributor.imecauthorKovalevich, Tatiana
dc.contributor.imecauthorThiam, Arame
dc.contributor.imecauthorVan Roey, Frieda
dc.contributor.imecauthorZografos, Odysseas
dc.contributor.orcidimecZografos, Odysseas::0000-0002-9998-8009
dc.date.accessioned2022-12-19T10:28:55Z
dc.date.available2022-09-19T02:51:17Z
dc.date.available2022-09-26T10:02:08Z
dc.date.available2022-12-19T10:28:55Z
dc.date.issued2022-05-26
dc.identifier.doi10.1117/12.2614260
dc.identifier.eisbn978-1-5106-4978-1
dc.identifier.isbn978-1-5106-4977-4
dc.identifier.issn0277-786X
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40464
dc.publisherSPIE-INT SOC OPTICAL ENGINEERING
dc.source.beginpage120510I
dc.source.conferenceConference on Optical and EUV Nanolithography XXXV Part of SPIE Advanced Conference
dc.source.conferencedateAPR 24-MAY 27, 2022
dc.source.conferencelocationSan Jose, California, United States
dc.source.journalSPIE Proceedings Vol. 12051: Optical and EUV Nanolithography XXXV
dc.source.numberofpages6
dc.source.volume12051
dc.subject.disciplineElectrical & electronic engineering
dc.title

Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

dc.typeProceedings paper
dspace.entity.typePublication
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