Publication:

Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology

Date

2014
Proceedings Paper
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dc.contributor.authorRoda Neve, Cesar
dc.contributor.authorRyckaert, Julien
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorDetalle, Mikael
dc.contributor.authorBeyne, Eric
dc.contributor.authorPantano, Nicolas
dc.contributor.authorVerhelst, Marian
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorDetalle, Mikael
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorPantano, Nicolas
dc.contributor.imecauthorVerhelst, Marian
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.contributor.orcidimecVerhelst, Marian::0000-0003-3495-9263
dc.date.accessioned2021-10-22T05:10:09Z
dc.date.available2021-10-22T05:10:09Z
dc.date.issued2014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24441
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6844528&sortType%3Dasc_p_Sequence%26filter%3DAND(p_IS_Number%3A684452
dc.source.beginpage1
dc.source.conferenceIEEE 18th Workshop on Signal and Power Integrity - SPI
dc.source.conferencedate11/05/2014
dc.source.conferencelocationGhent Belgium
dc.source.endpage4
dc.title

Investigation of chip-to-chip interconnections for memory-logic communication on 3D interposer technology

dc.typeProceedings paper
dspace.entity.typePublication
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