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The design of non-stacked and symmetric XOR for high-speed applications

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dc.contributor.authorPark, Minsu
dc.contributor.authorJin, Jahoon
dc.contributor.authorPark, Sehoon
dc.contributor.authorChun, jung-Hoon
dc.contributor.imecauthorPark, Sehoon
dc.contributor.orcidimecPark, Sehoon::0000-0002-9029-596X
dc.date.accessioned2023-11-06T11:26:52Z
dc.date.available2023-07-11T19:29:44Z
dc.date.available2023-11-06T11:26:52Z
dc.date.embargo2023-07-02
dc.date.issued2023
dc.description.wosFundingTextThis research was supported in part by Next-Generation Intelligence Semiconductor R & D Program (No. 20016216) and in part by the Fostering Global Talents for Innovative Growth Program (P0017312), funded by the Korea Ministry of Trade Industry and Energy, and in part by Samsung Electronics (IO201218-08229-01).
dc.identifier.doi10.1049/ell2.12850
dc.identifier.issn0013-5194
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42141
dc.publisherWILEY
dc.source.beginpageArt. e12850
dc.source.endpagena
dc.source.issue13
dc.source.journalELECTRONICS LETTERS
dc.source.numberofpages3
dc.source.volume59
dc.subject.keywordsFULL ADDER
dc.subject.keywordsLOW-POWER
dc.subject.keywordsXNOR
dc.title

The design of non-stacked and symmetric XOR for high-speed applications

dc.typeJournal article
dspace.entity.typePublication
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