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Impacts of process options on ESD device characteristics in sub-20nm bulk FinFET technology nodes

Date

2014-12
Meeting abstract
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dc.contributor.authorChen, Shih-Hung
dc.contributor.authorLee, Jam-Wem
dc.contributor.authorLinten, Dimitri
dc.contributor.authorScholz, Mirko
dc.contributor.authorSong, Ming-Hsiang
dc.contributor.authorHellings, Geert
dc.contributor.authorBoschke, Roman
dc.contributor.authorSibaja-Hernandez, Arturo
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorSibaja-Hernandez, Arturo
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.date.accessioned2021-10-22T00:55:18Z
dc.date.available2021-10-22T00:55:18Z
dc.date.issued2014-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23631
dc.source.beginpage514
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate15/12/2014
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage517
dc.title

Impacts of process options on ESD device characteristics in sub-20nm bulk FinFET technology nodes

dc.typeMeeting abstract
dspace.entity.typePublication
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