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Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Date

2016-10
Proceedings Paper
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dc.contributor.authorKarageorgos, Ioannis
dc.contributor.authorRyckaert, Julien
dc.contributor.authorGronheid, Roel
dc.contributor.authorTung, Maryann C.
dc.contributor.authorWong, H.-S. Philip
dc.contributor.authorKarageorgos, Evangelos
dc.contributor.authorBekaert, Joost
dc.contributor.authorVandenberghe, Geert
dc.contributor.authorDehaene, Wim
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorGronheid, Roel
dc.contributor.imecauthorBekaert, Joost
dc.contributor.imecauthorVandenberghe, Geert
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecBekaert, Joost::0000-0003-3075-3479
dc.date.accessioned2021-10-23T11:39:52Z
dc.date.available2021-10-23T11:39:52Z
dc.date.issued2016-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/26806
dc.source.conferenceInternational Symposium on DSA
dc.source.conferencedate11/10/2016
dc.source.conferencelocationGrenoble France
dc.title

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

dc.typeProceedings paper
dspace.entity.typePublication
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