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Gate-all-around nanowire FETs vs. triple-gate FinFETs: on gate integrity and device characteristics

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dc.contributor.authorVeloso, Anabela
dc.contributor.authorCho, Moon Ju
dc.contributor.authorSimoen, Eddy
dc.contributor.authorHellings, Geert
dc.contributor.authorMatagne, Philippe
dc.contributor.authorCollaert, Nadine
dc.contributor.authorThean, Aaron
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorThean, Aaron
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-23T16:31:07Z
dc.date.available2021-10-23T16:31:07Z
dc.date.embargo9999-12-31
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27512
dc.identifier.urlhttp://ecst.ecsdl.org/content/72/2/85.abstract
dc.source.beginpage85
dc.source.conferenceDielectrics for Nanosystems 7: Materials Science, Processing, Reliability, and Manufacturing
dc.source.conferencedate29/05/2016
dc.source.conferencelocationSan Diego, CA USA
dc.source.endpage95
dc.title

Gate-all-around nanowire FETs vs. triple-gate FinFETs: on gate integrity and device characteristics

dc.typeProceedings paper
dspace.entity.typePublication
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