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Threshold voltage model for deep-submicron fully-depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide

Date

2000
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dc.contributor.authorvan Meer, Hans
dc.contributor.authorDe Meyer, Kristin
dc.contributor.imecauthorDe Meyer, Kristin
dc.date.accessioned2021-10-14T14:02:09Z
dc.date.available2021-10-14T14:02:09Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4841
dc.source.conferenceEuropean Meeting on Silicon on Insulator Devices; 25-27 October 2000; Granada, Spain.
dc.source.conferencelocation
dc.title

Threshold voltage model for deep-submicron fully-depleted SOI CMOS transistors including the effect of source/drain fringing fields into the buried oxide

dc.typeOral presentation
dspace.entity.typePublication
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