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Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Publication:
Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
Date
2016
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Veloso, Anabela
;
Parvais, Bertrand
;
Matagne, Philippe
;
Simoen, Eddy
;
Huynh Bao, Trong
;
Paraschiv, Vasile
;
Vecchio, Emma
;
Devriendt, Katia
;
Rosseel, Erik
;
Ercken, Monique
;
Chan, BT
;
Delvaux, Christie
;
Altamirano Sanchez, Efrain
;
Versluijs, Janko
;
Tao, Zheng
;
Suhard, Samuel
;
Brus, Stephan
;
Sibaja-Hernandez, Arturo
;
Waldron, Niamh
;
Lagrain, Pieter
;
Richard, Olivier
;
Bender, Hugo
;
Vaisman Chasin, Adrian
;
Kaczer, Ben
;
Ivanov, Tsvetan
;
Ramesh, Siva
;
De Meyer, Kristin
;
Ryckaert, Julien
;
Collaert, Nadine
;
Thean, Aaron
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1988
since deposited on 2021-10-23
Acq. date: 2025-12-08
Citations
Metrics
Views
1988
since deposited on 2021-10-23
Acq. date: 2025-12-08
Citations