Publication:

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

Date

2016
Proceedings Paper
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dc.contributor.authorVeloso, Anabela
dc.contributor.authorParvais, Bertrand
dc.contributor.authorMatagne, Philippe
dc.contributor.authorSimoen, Eddy
dc.contributor.authorHuynh Bao, Trong
dc.contributor.authorParaschiv, Vasile
dc.contributor.authorVecchio, Emma
dc.contributor.authorDevriendt, Katia
dc.contributor.authorRosseel, Erik
dc.contributor.authorErcken, Monique
dc.contributor.authorChan, BT
dc.contributor.authorDelvaux, Christie
dc.contributor.authorAltamirano Sanchez, Efrain
dc.contributor.authorVersluijs, Janko
dc.contributor.authorTao, Zheng
dc.contributor.authorSuhard, Samuel
dc.contributor.authorBrus, Stephan
dc.contributor.authorSibaja-Hernandez, Arturo
dc.contributor.authorWaldron, Niamh
dc.contributor.authorLagrain, Pieter
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorParaschiv, Vasile
dc.contributor.imecauthorVecchio, Emma
dc.contributor.imecauthorDevriendt, Katia
dc.contributor.imecauthorRosseel, Erik
dc.contributor.imecauthorErcken, Monique
dc.contributor.imecauthorChan, BT
dc.contributor.imecauthorDelvaux, Christie
dc.contributor.imecauthorAltamirano Sanchez, Efrain
dc.contributor.imecauthorVersluijs, Janko
dc.contributor.imecauthorTao, Zheng
dc.contributor.imecauthorSuhard, Samuel
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorSibaja-Hernandez, Arturo
dc.contributor.imecauthorWaldron, Niamh
dc.contributor.imecauthorLagrain, Pieter
dc.contributor.imecauthorRichard, Olivier
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecDevriendt, Katia::0000-0002-0662-7926
dc.contributor.orcidimecChan, BT::0000-0003-2890-0388
dc.contributor.orcidimecLagrain, Pieter::0000-0003-3734-7203
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecVaisman Chasin, Adrian::0000-0002-9940-0260
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecIvanov, Tsvetan::0000-0003-3407-2742
dc.contributor.orcidimecRamesh, Siva::0000-0002-8473-7258
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-23T16:32:39Z
dc.date.available2021-10-23T16:32:39Z
dc.date.issued2016
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27514
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7573409
dc.source.beginpage138
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate13/06/2016
dc.source.conferencelocationHonolulu, HI USA
dc.source.endpage139
dc.title

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

dc.typeProceedings paper
dspace.entity.typePublication
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