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A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node

Date

2015
Proceedings Paper
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dc.contributor.authorRedolfi, Augusto
dc.contributor.authorGoux, Ludovic
dc.contributor.authorJossart, Nico
dc.contributor.authorYamashita, Fumiko
dc.contributor.authorNishimura, Eiichi
dc.contributor.authorUrayama, Daisuke
dc.contributor.authorFujimoto, Kiwamu
dc.contributor.authorWitters, Thomas
dc.contributor.authorLazzarino, Frederic
dc.contributor.authorJurczak, Gosia
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorGoux, Ludovic
dc.contributor.imecauthorJossart, Nico
dc.contributor.imecauthorWitters, Thomas
dc.contributor.imecauthorLazzarino, Frederic
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecGoux, Ludovic::0000-0002-1276-2278
dc.contributor.orcidimecLazzarino, Frederic::0000-0001-7961-9727
dc.date.accessioned2021-10-22T22:10:28Z
dc.date.available2021-10-22T22:10:28Z
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25808
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7223718
dc.source.beginpage134
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate15/06/2015
dc.source.conferencelocationKyoto Japan
dc.source.endpage135
dc.title

A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node

dc.typeProceedings paper
dspace.entity.typePublication
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