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At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

Date

2015-11
Proceedings Paper
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dc.contributor.authorShibin, Konstantin
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorPapameletis, Christos
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2021-10-22T22:49:17Z
dc.date.available2021-10-22T22:49:17Z
dc.date.issued2015-11
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25899
dc.source.conferenceIEEE Asian Test Symposium - ATS
dc.source.conferencedate22/11/2015
dc.source.conferencelocationMumbai India
dc.title

At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic

dc.typeProceedings paper
dspace.entity.typePublication
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