Publication:

Influence of gate length on ESD performance for deep submicron CMOS technology

Date

1999
Proceedings Paper
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dc.contributor.authorBock, Karlheinz
dc.contributor.authorKeppens, Bart
dc.contributor.authorDe Heyn, Vincent
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorChing, L. Y.
dc.contributor.authorNaem, Abdalla
dc.contributor.imecauthorDe Heyn, Vincent
dc.contributor.imecauthorGroeseneken, Guido
dc.date.accessioned2021-10-06T10:43:16Z
dc.date.available2021-10-06T10:43:16Z
dc.date.embargo9999-12-31
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3240
dc.source.beginpage95
dc.source.conferenceElectrical Overstress/Electrostatic Discharge Symposium Proceedings - EOS-ESD
dc.source.conferencedate28/09/1999
dc.source.conferencelocationOrlando, FL USA
dc.source.endpage104
dc.title

Influence of gate length on ESD performance for deep submicron CMOS technology

dc.typeProceedings paper
dspace.entity.typePublication
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