Publication:
Test circuits for fast and reliable assessment if CDM robustness of I/O stages
Date
| dc.contributor.author | Stadler, W. | |
| dc.contributor.author | Esmark, K. | |
| dc.contributor.author | Reynders, K. | |
| dc.contributor.author | Zubeidat, M. | |
| dc.contributor.author | Graf, M. | |
| dc.contributor.author | Wilkening, W. | |
| dc.contributor.author | Willemen, J. | |
| dc.contributor.author | Qu, D. | |
| dc.contributor.author | Mettler, S. | |
| dc.contributor.author | Etherton, M. | |
| dc.contributor.author | Nuernbergk, D. | |
| dc.contributor.author | Wolf, H. | |
| dc.contributor.author | Gieser, H. | |
| dc.contributor.author | Soppa, W. | |
| dc.contributor.author | De Heyn, Vincent | |
| dc.contributor.author | Mahadeva Iyer, Natarajan | |
| dc.contributor.author | Groeseneken, Guido | |
| dc.contributor.author | Morena, E. | |
| dc.contributor.author | Stella, I. | |
| dc.contributor.author | Andreini, A. | |
| dc.contributor.imecauthor | De Heyn, Vincent | |
| dc.contributor.imecauthor | Groeseneken, Guido | |
| dc.date.accessioned | 2021-10-16T05:24:05Z | |
| dc.date.available | 2021-10-16T05:24:05Z | |
| dc.date.issued | 2005 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/11266 | |
| dc.source.beginpage | 269 | |
| dc.source.endpage | 277 | |
| dc.source.issue | 2 | |
| dc.source.journal | Microelectronics Reliability | |
| dc.source.volume | 45 | |
| dc.title | Test circuits for fast and reliable assessment if CDM robustness of I/O stages | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
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