Publication:

Defect and Fault Modeling Framework for STT-MRAM Testing

Date

2021
Journal article
https://doi.org/10.1109/TETC.2019.2960375
Simple item page Full metadata Statistics
 
dc.contributor.authorWu, Lizhou
dc.contributor.authorRao, Siddharth
dc.contributor.authorTaouil, Mottaqiallah
dc.contributor.authorMedeiros, Guilherme Cardoso
dc.contributor.authorFieback, Moritz
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorHamdioui, Said
dc.contributor.imecauthorRao, Siddharth
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.orcidextTaouil, Mottaqiallah::0000-0002-9911-4846
dc.contributor.orcidextFieback, Moritz::0000-0002-9782-393X
dc.contributor.orcidextHamdioui, Said::0000-0002-8961-0387
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned2022-03-03T14:23:17Z
dc.date.available2022-03-03T14:23:17Z
dc.date.issued2021
dc.identifier.doi10.1109/TETC.2019.2960375
dc.identifier.issn2168-6750
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39277
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage707
dc.source.endpage723
dc.source.issue2
dc.source.journalIEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
dc.source.numberofpages17
dc.source.volume9
dc.subject.keywordsTUNNEL-JUNCTION STACKS
dc.subject.keywordsRESISTIVE-OPEN
dc.subject.keywordsCOMPACT MODEL
dc.subject.keywordsBREAKDOWN
dc.subject.keywordsDESIGN
dc.title

Defect and Fault Modeling Framework for STT-MRAM Testing

dc.typeJournal article
dspace.entity.typePublication
Files
Publication available in collections:
Articles